In the Linux kernel, the following vulnerability has been resolved:
spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.
CVSS
No CVSS.
References
Configurations
No configuration.
History
19 Aug 2024, 12:59
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Summary |
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17 Aug 2024, 09:15
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New CVE |
Information
Published : 2024-08-17 09:15
Updated : 2024-08-19 12:59
NVD link : CVE-2024-42279
Mitre link : CVE-2024-42279
CVE.ORG link : CVE-2024-42279
JSON object : View
Products Affected
No product.
CWE
No CWE.