CVE-2025-45006

{"id": "CVE-2025-45006", "cveTags": [], "metrics": {"cvssMetricV31": [{"type": "Secondary", "source": "134c704f-9b21-4f2e-91b3-4a467353bcc0", "cvssData": {"scope": "UNCHANGED", "version": "3.1", "baseScore": 9.1, "attackVector": "NETWORK", "baseSeverity": "CRITICAL", "vectorString": "CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H", "integrityImpact": "NONE", "userInteraction": "NONE", "attackComplexity": "LOW", "availabilityImpact": "HIGH", "privilegesRequired": "NONE", "confidentialityImpact": "HIGH"}, "impactScore": 5.2, "exploitabilityScore": 3.9}]}, "published": "2025-07-01T20:15:24.993", "references": [{"url": "https://github.com/chipsalliance/rocket-chip.git", "source": "cve@mitre.org"}, {"url": "https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md", "source": "cve@mitre.org"}, {"url": "https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications", "source": "cve@mitre.org"}], "vulnStatus": "Awaiting Analysis", "weaknesses": [{"type": "Secondary", "source": "134c704f-9b21-4f2e-91b3-4a467353bcc0", "description": [{"lang": "en", "value": "CWE-266"}]}], "descriptions": [{"lang": "en", "value": "Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks."}, {"lang": "es", "value": "La retenci\u00f3n incorrecta de bits de mstatus.SUM (distinta de cero) en el commit f517abb del procesador RISC-V de c\u00f3digo abierto viola las restricciones de especificaci\u00f3n privilegiada, lo que permite posibles ataques de acceso a la memoria f\u00edsica."}], "lastModified": "2025-07-03T15:14:12.767", "sourceIdentifier": "cve@mitre.org"}